1. Field of the Invention
This application relates to divider circuits and more particularly to programmable divider circuits useful for dividing high-speed signals.
2. Description of the Related Art
Many applications use divider circuits to divide high-speed clock signals. In order to provide flexibility, programmable divider circuits may be preferred in some applications. Several approaches for such programmable divider circuits are known in the art. For example, FIG. 1 illustrates a programmable divider based on a conventional dual modulus prescalar. The output frequency
      f    out    =                    f        in                              R          ⁡                      (                          P              +              1                        )                          +                              (                          Q              -              R                        )                    ⁢          P                      =                            f          in                          QP          +          R                    .      Several aspects of the divider circuit illustrated in FIG. 1 may make it undesirable for certain applications. For example, the feedback loop around P/(P+1) limits the maximum possible speed of the divider circuit and thus the speed of the signals that can be divided. Additionally, the clock input will be loaded by (log2 P+1) flip-flops. Also, synchronization circuitry is required to change the modulus and reset the counters correctly.
Another prior art approach is illustrated in FIG. 2, which shows a programmable divider based on a loadable backward counter. The circuit includes a loadable backward counter 201 with a zero detect circuit 203. The feedback loop formed by the first-stage SR counter, the zero detector, the load signal (with high fanout) may limit the maximum possible speed of the divider circuit in certain applications.
Accordingly, there is a need for an improved programmable divide circuit.